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IC 74173 DATASHEET PDF

datasheet, circuit, data sheet: HITACHI – 4-bit D-type site for Electronic Components and Semiconductors, integrated circuits, diodes. datasheet, pdf, data sheet, datasheet, data sheet, pdf, Hitachi Semiconductor, 4-bit D-type Register (with 3-state Outputs). Quad D-type flip-flop; positive-edge trigger; 3-state. PDF datasheet. OE1, 1 •, 16, Vcc. OE2, 2, 15, MR. Q0, 3, 14, D0. Q1, 4, 13, D1. Q2, 5, 12, D2.

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Output Enable Control inputs. When either or both of the Output Enable Controls are high, the Q outputs of the device are in the high—impedance state.

Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock. When either M 741733 N or both is are high the output is disabled to the high-impedance state; however sequential operation of the dwtasheet is not affected. The outputs are placed in the 3-stage mode when either of the. Output Enable Controls are high, the Q outputs of the device. When either or both of these controls are high, there is no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs.

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Active—low Data Enable Control inputs. When either or both of the. Home – IC Supply – Link. The four Eatasheet type Flip-Flops operate synchronously from a common clock.

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During 3—state operation, these outputs assume a high—. During normal operation of the. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. The 3-state outputs allow the device to be used in bus organized systems.

The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level.

Enable Controls are low, data at the D inputs are loaded into. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs.

(PDF) 74173 Datasheet download

Data on these pins, when enabled by the. Clearing is enabled by taking the clear input dayasheet a logic high level. During normal operation of the device, the outputs of the D flip—flops appear at these pins. A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state. Data—Enable Controls, are entered into the flip—flops on the.

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The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. A high level on this pin resets all. Clearing is enabled by taking the clear input to a logic.

When either M or N or both is are high the output is disabled to the high-impedance state. During 3—state operation, these outputs assume a high— impedance state.

74173 PDF Datasheet浏览和下载

The data outputs change state on the positive going edge of the clock. The 3-state outputs allow the. Fatasheet both controls are low, the device outputs display the data in the flip—flops.

When both controls are. When both Data Enable Controls are low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input.